DownloadHDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL
License
GNU General Public License version 2.0 (GPLv2)Follow sim-sim
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User Reviews
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sim-sim is perfect tool for synthesis, although I have noticed some problems with output formatting, netlist optimalization and absence of documentation.
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This is AWESOME indeed. But it is hard to find and it really could use some documentation...
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Sim-sim works excellent.
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This project is AWESOME! Please present it more prominently so others can find it easier. At first I didn't try it because there was so little information here..